The present invention relates to a ferroelectric-type nonvolatile semiconductor memory (so-called FERAM).
In recent years, studies are actively made with regard to a ferroelectric-type nonvolatile semiconductor memory having a large capacity. A ferroelectric-type nonvolatile semiconductor memory (to be sometimes abbreviated as xe2x80x9cnonvolatile memoryxe2x80x9d hereinafter) permits rapid access and is nonvolatile and small, and it consumes less electric power and has strength against an impact, so that it is expected to be used as a main storage device in various electronic machines and equipment having functions of file storage and resume, such as a portable computer, a cellular phone and a game machine, or as a recording medium for recording voices or images.
The above nonvolatile memory is a fast rewritable nonvolatile memory according to a method in which a change in an accumulated charge amount in a capacitor member having a ferroelectric layer is detected by utilizing fast polarization inversion and residual polarization of the ferroelectric layer, and the nonvolatile memory basically comprises the memory cell (capacitor member) and a transistor for selection (transistor for switching). The memory cell (capacitor member) comprises, for example, a lower electrode, an upper electrode and the ferroelectric layer interposed between these electrodes. Data is written into and read out from the above nonvolatile memory by using the P-E (V) hysteresis loop of the ferroelectric layer shown in FIG. 23. That is, when an external electric field is applied to the ferroelectric layer and then removed, the ferroelectric layer exhibits residual polarization. When an external electric field in the plus direction is applied, the residual polarization of the ferroelectric layer comes to be +Pr, and when an external electric field in the minus direction is applied, it comes to be xe2x88x92Pr. When the residual polarization is in the state of +Pr (see xe2x80x9cDxe2x80x9d in FIG. 23), such a state represents xe2x80x9c0xe2x80x9d, and when the residual polarization is in the state of xe2x88x92Pr (see xe2x80x9cAxe2x80x9d in FIG. 23), such a state represents xe2x80x9c1xe2x80x9d.
For discriminating the state of xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d, an external electric field, for example, in the plus direction is applied to the ferroelectric layer, whereby the polarization of the ferroelectric layer comes into the state of xe2x80x9cCxe2x80x9d in FIG. 23. In this case, when the data is xe2x80x9c0xe2x80x9d, the polarization state of the ferroelectric layer changes from the state of xe2x80x9cDxe2x80x9d to the state of xe2x80x9cCxe2x80x9d. When the data is xe2x80x9c1xe2x80x9d, the polarization state of the ferroelectric layer changes from the state of xe2x80x9cAxe2x80x9d to the state of xe2x80x9cCxe2x80x9d through the state of xe2x80x9cBxe2x80x9d. When the data is xe2x80x9c0xe2x80x9d, the polarization inversion does not take place in the ferroelectric layer. When the date is xe2x80x9c1xe2x80x9d, the polarization inversion takes place in the ferroelectric layer. As a result, there is caused a difference in the accumulated charge amount in the memory cell (capacitor member). The above accumulated charge is detected as a signal current by bringing, into an ON-state, the transistor for selection in a selected nonvolatile memory. When the external electric field is brought into 0 after data is read out, the polarization state of the ferroelectric layer comes into the state of xe2x80x9cDxe2x80x9d in FIG. 23 both when the data is xe2x80x9c0xe2x80x9d and when it is xe2x80x9c1xe2x80x9d. That is, when the data is read out, the data xe2x80x9c1xe2x80x9d is once destroyed. When the data is xe2x80x9c1xe2x80x9d, therefore, the polarization is brought into the state of xe2x80x9cAxe2x80x9d through xe2x80x9cDxe2x80x9d and xe2x80x9cExe2x80x9d by applying the external electric field in the minus direction, to re-write data xe2x80x9c1xe2x80x9d.
ABO3 type ferroelectric oxides such as lead titanate zirconate [PZT, Pb(Zr,Ti)3] and lanthanum lead titanate zirconate [(Pb,La)(Zr,Ti)O3] have been mainly developed as a ferroelectric material for constituting the ferroelectric layer, and part of them has been put to practical use in a nonvolatile memory.
The structure and the operation of a currently mainstream nonvolatile memory are proposed by S. Sheffiled et al. in U.S. Pat. No. 4,873,664. The above nonvolatile memory comprises two nonvolatile memory cells as shown in a circuit diagram of FIG. 24. In FIG. 24, each nonvolatile memory is surrounded by a dotted line. Each nonvolatile memory comprises, for example, transistors for selection TR11 and TR12 and memory cells (capacitor members) FC11 and FC12.
Concerning two-digit or three-digit subscripts, for example, a subscript xe2x80x9c11xe2x80x9d is a subscript that should be shown as xe2x80x9c1,1xe2x80x9d, and for example, a subscript xe2x80x9c111xe2x80x9d is a subscript that should be shown as xe2x80x9c1,1,1xe2x80x9d. For simplified showing, the subscripts are shown as two-digit or three-digit subscripts. Further, a subscript xe2x80x9cMxe2x80x9d is used to show, for example, a plurality of memory cells or plate lines in the block, and a subscript xe2x80x9cmxe2x80x9d is used to show an individual, for example, of a plurality of the memory cells or the plate lines. A subscript xe2x80x9cNxe2x80x9d is used to show, for example, transistors for selection or memory units in the block, and a subscript xe2x80x9cnxe2x80x9d is used to show, for example, an individual of the transistors for selection or the memory units.
Complementary data is written into a pair of the memory cells, and the nonvolatile memory stores 1 bit. In FIG. 24, symbol xe2x80x9cWLxe2x80x9d stands for a word line, symbol xe2x80x9cBLxe2x80x9d stands for a bit line, and symbol xe2x80x9cPLxe2x80x9d stands for a plate line. When one nonvolatile memory is taken, the word line WL1 is connected to a word line decoder/driver WD. The bit lines BL1 and BL2 are connected to a sense amplifier SA. Further, the plate line PL1 is connected to a plate line decoder/driver PD.
When the stored data is read out from the thus-structured nonvolatile memory, the word line WL1 is selected, and further, the plate line PL1 is driven. In this case, the complementary data appears on a pair of the bit lines BL1 and BL2 as voltages (bit line potentials) from a pair of the memory cells (capacitor members) FC11 and FC12 through the transistors for selection TR11, and TR12. The voltages (bit line potentials) on the pair of the bit lines BL1 and BL2 are detected with the sense amplifier SA.
One nonvolatile memory occupies a region surrounded by the word line WL1 and a pair of the bit lines BL1 and BL2. If the word lines and the bit lines are arranged at a smallest pitch, therefore, the smallest area of one nonvolatile memory is 8F2 when the minimum fabrication dimension is xe2x80x9cFxe2x80x9d. Therefore, the thus-structured nonvolatile memory has a smallest area of 8F2.
When it is attempted to increase the capacity of the above-structured nonvolatile memories, its realization can only rely on minuteness of fabrication dimension. Constitution of one nonvolatile memory requires two transistors for selection and two memory cells (capacitor members). Further, it is required to arrange the plate lines at the same pitch as that at which the word lines are arranged. It is therefore almost impossible to arrange the nonvolatile memories at the minimum pitch, and in reality, the area that one nonvolatile memory occupies comes to be much greater than 8F2.
Moreover, it is also required to arrange the word line decoders/drivers WD and the plate line decoders/drivers PD at a pitch equal to a pitch at which the nonvolatile memories are arranged. In other words, two decoders/drivers are required for selecting one low-address. It is therefore difficult to layout peripheral circuits, and the area that the peripheral circuits occupy comes to be large.
One means for decreasing an area of a nonvolatile memory is disclosed in JP-A-121032/1997. As FIG. 25 shows a circuit diagram, the nonvolatile memory disclosed in the above Laid-open comprises a plurality of memory cells MC1M (for example, M=4) one end of each of which is connected to one end of one transistor for selection TR1 in parallel, and a plurality of memory cells MC2M one end of each of which is connected to one end of one transistor for selection TR2 in parallel. The other ends of the transistors for selection TR1 and TR2 are connected to bit lines BL1 and BL2, respectively. The paired bit lines BL1 and BL2 are connected to a sense amplifier SA. Further, the other end of each of the paired memory cells MC1m, MC2m (m=1, 2 . . . M) is connected to a common plate line PLm, and the plate line PLm, is connected to a plate line decoder/driver PD. Further, the word line WL is connected to a word line decoder/driver WD.
Complementary data is stored in a pair of the memory cells MC1m and MC2m (m=1, 2 . . . M). For reading out the data stored, for example, in the memory cells MC1m and MC2m (wherein m is one of 1, 2, 3 and 4), the word line WL is selected, and the plate line PLm is driven in a state where a voltage of (xc2xd)Vcc or (⅓)Vcc is applied to the plate lines PLj (mxe2x89xa0j). The above Vcc is, for example, a power source voltage. By the above procedure, the complementary data appears on a pair of the bit lines BL1 and BL2 as voltages (bit line potentials) from a pair of the memory cells MC1m and MC2m through the transistors for selection TR1 and TR2. And, the sense amplifier SA detects the voltages (bit line potentials) on the pair of the bit lines BL1 and BL2.
A pair of the transistors for selection TR1 and TR2 in the paired nonvolatile memories occupy a region surrounded by the word lines WL and a pair of the bit lines BL1 and BL2. If the word lines and the bit lines are arranged at a smallest pitch, therefore, a pair of the transistors for selection TR1 and TR2 in the paired nonvolatile memories have a minimum area of 8F2. Since, however, a pair of the transistors for selection TR1 and TR2 are shared by M sets of pairs of the memory cells MC1m and MC2m (m=1, 2 . . . M), the number of the transistors for selection TR1 and TR2 per bit can be decreased, and the layout of the word lines WL is moderate, so that the nonvolatile memory can be easily decreased in size. Further, with regard to the peripheral circuits, M bits can be selected with one word line decoder/driver WD and the plate line decoders/drivers PD that are M in number. When the above constitution is employed, therefore, the layout in which the cell area is close to 8F2 can be attained, and a chip size almost equal to a DRAM can be attained.
The method of decreasing the area of a nonvolatile memory, disclosed in JP-A-121032/1997, is very effective, but has the following problem.
That is, when data xe2x80x9c1xe2x80x9d is written into the memory cell MC11 in a pair of the memory cells MC11 and MC21, the plate line PL1 is brought to a ground level (0 volt), and Vcc is applied to the bit line BL1, to polarize the ferroelectric layer. In this case, it is required to bring the bit line BL2 to a ground level (0 volt) for retaining data xe2x80x9c0xe2x80x9d in the memory cell MC21.
For preventing destruction of data stored in the memory cells MC1m and MC2m (m=2, 3, 4) connected to non-selected plate lines PLm (m=2, 3, 4), the potential of the non-selected plate lines PLm (m=2, 3, 4) is fixed at (xc2xd) Vcc or (⅓) Vcc that is an intermediate potential between the bit lines BL1 and BL2, to ease or relax the electric field that is to be applied to the ferroelectric layer constituting the non-selected memory cells MC1m and MC2m. That is, disturbance of (xc2xd) Vcc or (⅓) Vcc is exerted on the non-selected memory cells MC1m and MC2m. The above disturbance refers to a phenomenon in which an electric field is exerted on a ferroelectric layer constituting a non-selected memory cell in a direction in which the polarization is inverted, that is, a direction in which data stored is deteriorated or destroyed. When the nonvolatile memory is composed of the memory cells that are M in number, the number of times of disturbance exerted on one memory cell is (Mxe2x88x921) times. Each memory cell is therefore required to retain a sufficient signal amount (accumulated charge) after it suffers disturbance (Mxe2x88x921) times.
However, in conventional nonvolatile memories typified by the nonvolatile memory disclosed in U.S. Pat. No. 4,873,664, no memory cells are caused to have any disturbance, so that nothing is taken into account with regard to disturbance durability as a property required of a ferroelectric material. When a ferroelectric material used for a conventional nonvolatile memory, such as PZT, is applied to a nonvolatile memory that structurally suffers disturbance, therefore, there is involved a problem that no sufficient disturbance durability is attained.
It is therefore an object of the present invention to optimize the composition of a ferroelectric material for constituting a ferroelectric layer in a ferroelectric-type nonvolatile semiconductor memory that essentially structurally suffers disturbance, so that there can be provided a ferroelectric-type nonvolatile semiconductor memory having high durability against disturbance.
A ferroelectric-type nonvolatile semiconductor memory according to a first aspect of the present invention for achieving the above object comprises;
(A) a bit line,
(B) a transistor for selection,
(C) a memory unit composed of memory cells that are M in number (Mxe2x89xa72), and
(D) plate lines that are M in number,
in which each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
in the memory unit, the first electrodes of the memory cells are in common, said common first electrode is connected to the bit line through the transistor for selection,
in the memory unit, the second electrode of the m-th-place (m=1, 2 . . . , M) memory cell is connected to the m-th-place plate line,
the ferroelectric layer constituting each memory cell is composed of lead titanate zirconate [Pb(ZrX,TiY)O3], and
said lead titanate zirconate has a composition that satisfies 0.6 less than Y/(X+Y)xe2x89xa60.9.
A ferroelectric-type nonvolatile semiconductor memory according to a second aspect of the present invention for achieving the above object comprises;
(A) a bit line,
(B) a transistor for selection,
(C) memory units that are N in number (Nxe2x89xa72), each memory unit being composed of memory cells that are M in number (Mxe2x89xa72), and
(D) plate lines that are Mxc3x97N in number,
in which the memory units that are N in number are stacked through an insulating interlayer,
each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
in each memory unit, the first electrodes of the memory cells are in common, said common first electrode is connected to the bit line through the transistor for selection,
in the memory unit of the n-th layer (n=1, 2 . . . , N), the second electrode of the m-th-place (m=1, 2 . . . , M) memory cell is connected to the [(nxe2x88x921)M+m]-th-place plate line,
the ferroelectric layer constituting each memory cell is composed of lead titanate zirconate [Pb(ZrX,TiY)O3], and
said lead titanate zirconate has a composition that satisfies 0.6 less than Y/(X+Y)xe2x89xa60.9.
A ferroelectric-type nonvolatile semiconductor memory according to a third aspect of the present invention for achieving the above object comprises;
(A) a bit line,
(B) transistors for selection that are N in number (Nxe2x89xa72),
(C) N memory units that are N in number, each memory unit being composed of memory cells that are M in number (Mxe2x89xa72), and
(D) plate lines that are M in number,
in which the memory units that are N in number are stacked through an insulating interlayer,
each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
in each memory unit, the first electrodes of the memory cells are in common,
in the memory unit of the n-th layer (n=1, 2 . . . , N), the common first electrode is connected to the bit line through the n-th-place transistor for selection,
in the memory unit of the n-th layer, the second electrode of the m-th-place (m=1, 2 . . . , M) memory cell is connected to the m-th-place plate line common to the memory units,
the ferroelectric layer constituting each memory cell is composed of lead titanate zirconate [Pb(ZrX,TiY)O3], and
said lead titanate zirconate has a composition that satisfies 0.6 less than Y/(X+Y)xe2x89xa60.9.
A ferroelectric-type nonvolatile semiconductor memory according to a fourth aspect of the present invention for achieving the above object comprises;
(A) bit lines that are N in number (Nxe2x89xa72),
(B) transistors for selection that are N in number,
(C) memory units that are N in number, each memory cell being composed of memory cells that are M in number (Mxe2x89xa72), and
(D) plate lines that are M in number,
in which the memory units that are N in number are stacked through an insulating interlayer,
each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
in each memory unit, the first electrodes of the memory cells are in common,
in the memory unit of the n-th layer (n=1, 2 . . . , N), the common first electrode is connected to the n-th-place bit line through the n-th-place transistor for selection,
in the memory unit of the n-th layer, the second electrode of the m-th-place (m=1, 2 . . . , M) memory cell is connected to the m-th-place plate line common to the memory units,
the ferroelectric layer constituting each memory cell is composed of lead titanate zirconate [Pb(ZrX,TiY)O3], and
said lead titanate zirconate has a composition that satisfies 0.6 less than Y/(X+Y)xe2x89xa60.9.
In the ferroelectric-type nonvolatile semiconductor memories according to the first to fourth aspects of the present invention (these will be sometimes simply generally referred to as xe2x80x9cnonvolatile memory of the present inventionxe2x80x9d hereinafter), a lead titanate zirconate (to be sometimes called xe2x80x9cPZTxe2x80x9d for short hereinafter) that has a perovskite structure and is a solid solution of lead titanate [PbTiO3] and lead zirconate [PbZrO3] has a composition that satisfies 0.6 less than Y/(X+Y)xe2x89xa60.9, whereby the ferroelectric layer can have a sufficiently large coercive electric field, a well-rectangular P-E(V) hysteresis loop and a sufficiently large residual polarization xc2x1Pr, so that the memory cells are improved in disturbance durability. For further improving the disturbance durability and preventing an increase in leak current or deterioration of dielectric strength, preferably, the above composition satisfies 0.7 less than Y/(X+Y)xe2x89xa60.85. When the above expression is Y/(X+Y)xe2x89xa60.6, no excellent disturbance durability can be obtained. When it is 0.9 less than Y/(X+Y), the leak current increases or the dielectric strength is deteriorated.
Concerning whether or not the composition of PZT satisfies 0.6 less than Y/(X+Y)xe2x89xa60.9, the composition can be analyzed by a physical analysis method such as a fluorescence X-ray analysis method or an EPMA (Electron Problem Micro Analysis) method or by a chemical analysis method such as an ICP (Inductively Coupled Plasma) method or general chemical analysis.
In the nonvolatile memory according to any one of the second to fourth aspects of the present invention, since one transistor for selection is shared by a plurality of the memory cells and the memory units have the three-dimensional stack structure, a limitation imposed by the number of transistors occupying the semiconductor substrate surface is removed, the storage capacity can be remarkably enhanced as compared with any conventional ferroelectric-type nonvolatile semiconductor memory, and the effective occupation area of bit storage units can be greatly decreased. Address selection in the row direction is performed by means of a two-dimensional matrix composed of the transistors for selection and the plate lines. For example, when a row address selection unit is composed of 8 transistors for selection and 8 plate lines, 64-bit memory cells can be selected with 16 decoder/driver circuits. Even when the integration degree of a ferroelectric-type nonvolatile semiconductor memory is equal to that of a conventional ferroelectric-type nonvolatile semiconductor memory, the storage capacity can be quadrupled. Further, the number of peripheral circuits and driving wirings for address selection can be reduced.
In the nonvolatile memory of the present invention, it is sufficient to satisfy Mxe2x89xa72, and for example, the practical value of M includes exponents of 2 (2, 4, 8 . . . ). Further, in the nonvolatile memory according to any one of the second to fourth aspects of the present invention, it is sufficient to satisfy Nxe2x89xa72, and for example, the practical value of N includes exponents of 2 (2, 4, 8 . . . ).
The PZT in the present invention includes PLZT [(Pb,La)(ZrX,TiY)O3] that is a metal oxide obtained by adding lanthanum (La) to PZT, PNZT[(Pb,Nb)(ZrX,TiY)O3] that is a metal oxide obtained by adding niobium (Nb) to PZT, PCZT[(Pb,Ca)(ZrX,TiY)O3] that is a metal oxide obtained by adding calcium (Ca) to PZT, PSZT[(Pb,Sr)(ZrX,TiY)O3] that is a metal oxide obtained by adding strontium (Sr) to PZT, and mixtures of these metal oxides. PLZT, PNZT, PCZT, PSZT and mixtures of these have compositions that satisfy 0.6 less than Y/(X+Y)xe2x89xa60.9.
The ferroelectric layer can be obtained by patterning the ferroelectric thin film in a step following the formation of the ferroelectric thin film. In some cases, the patterning of the ferroelectric thin film is not required. The ferroelectric thin film can be formed, for example, by a method such as a sputtering method including a magnetron sputtering method and a reactive sputtering method; a pulse laser abrasion method; an electron beam deposition method; a solution chemical deposition method (sol-gel method) including a spraying method and a spin-coating method; an MOCVD method; and an LSMCD (Liquid Source Mist Chemical Deposition) method. The ferroelectric thin film can be patterned, for example, by an anisotropic ion etching (RIE) method.
The crystalline orientation of PZT constituting the ferroelectric layer is preferably a unidirectional orientation, particularly preferably a (111) unidirectional orientation. PZT satisfying 0.6 less than Y/(X+Y)xe2x89xa60.9 is a so-called Ti-rich PZT, and such a PZT has the crystal structure of a cubic system. When the crystal orientation of PZT is a (111) unidirectional orientation, excellent switching characteristics can be obtained, and as a result, excellent disturbance durability can be attained.
For obtaining a highly reliable ferroelectric layer, preferably, the PZT constituting the ferroelectric layer has a density of 6750 kg/m3 (6.75 g/cm3) to 8000 kg/m3 (8.9 g/cm3).
In the present invention, there may be employed a constitution in which the first electrode is formed below the ferroelectric layer and the second electrode is formed on the ferroelectric layer (that is, the first electrode corresponds to the lower electrode and the second electrode corresponds to the upper electrode), or there may be employed a constitution in which the first electrode is formed on the ferroelectric layer and the second electrode is formed below the ferroelectric layer (that is, the first electrode corresponds to the upper electrode and the second electrode corresponds to the lower electrode). There may be employed a constitution in which the plate line extends from the second electrode, or there may be employed a constitution in which the plate line is formed separately from the second electrode and is connected to the second electrode. In the latter case, the wiring material for constituting the plate line includes, for example, aluminum and an aluminum-containing alloy.
The structure in which the first electrodes are in common specifically includes a structure in which the first electrode in the form of a stripe is formed and the ferroelectric layer is formed on the entire surface of the first electrode in the form of a stripe. In the above structure, an overlapping region of the first electrode, the ferroelectric layer and the second electrode corresponds to the memory cell. Alternatively, the structure in which the first electrodes are in common includes a structure in which ferroelectric layers are formed on predetermined regions of the first electrode and the second electrodes are formed on the ferroelectric layers, and a structure in which the first electrodes are formed in predetermined surface regions of a wiring layer, the ferroelectric layers are formed on the first electrodes and the second electrodes are formed on the ferroelectric layers, although the above structure shall not be limited thereto.
In the present invention, desirably, the first electrode and the second electrode are formed of at least one metal selected from platinum group metals or oxide thereof, or formed of at least one metal selected from the group consisting of ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt) and rhenium (Re) or oxide thereof. Specific examples of the above metals or oxides include Ir, IrO2xe2x88x92X, IrO2xe2x88x92X/Ir, Ir/IrO2xe2x88x92X, SrIrO3, Ru, RuO2xe2x88x92X, SrRuO3, Pt, Pt/IrO2xe2x88x92X, Pt/RuO2xe2x88x92X, Pd, a Pt/Ti stacked structure, a Pt/Ta stacked structure, a Pt/Ti/Ta stacked structure, La0.5Sr0.5CoO3(LSCO), a Pt/LSCO stacked structure and YBa2Cu3O7. In the above chemical formulae, the value of X satisfies 0xe2x89xa6X less than 2. In the above stacked structures, a material positioned after xe2x80x9c/xe2x80x9d is in contact with the ferroelectric layer. The first electrode and the second electrode may be formed of one material, materials of the same kind or materials of different kinds. For forming the first electrode or the second electrode, a first electrically conductive material layer or a second electrically conductive material layer is formed, and in a step to come thereafter, the first electrically conductive material layer or the second electrically conductive material layer is patterned. The first electrically conductive material layer or the second electrically conductive material layer can be formed by a method properly suitable for the materials for constituting the first electrically conductive material layer or the second electrically conductive material layer, such as a sputtering method, a reactive sputtering method, an electron beam deposition method, an MOCVD method or a pulse laser abrasion method. The first electrically conductive material layer or the second electrically conductive material layer can be patterned, for example, by an ion milling method or an RIE method.
In the nonvolatile memory of the present invention, further, when the first electrode is formed below the ferroelectric layer and when the second electrode is formed on the ferroelectric layer, the first electrode constituting the memory cell preferably has a so-called damascene structure. When the first electrode is formed on the ferroelectric layer and when the second electrode is formed below the ferroelectric layer, the second electrode constituting the memory cell preferably has a so-called damascene structure. That is because the ferroelectric layer can be formed on a flat substratum.
In the present invention, the material for constituting the insulating interlayer includes silicon oxide (SiO2), silicon nitride (SiN), SiON, SOG, NSG, BPSG, PSG, BSG and LTO.
The transistor for selection (transistor for switching) and various transistors formed in a semiconductor substrate below the memory cells through an insulating layer can be constituted, for example, of a known MIS type FET or MOS type FET. The material for the bit line includes polysilicon doped with an impurity or a refractory metal material. The common first electrode and the transistor for selection can be electrically connected to each other through a contact hole made through the insulating layer interposed between the common first electrode and the transistor for selection or can be electrically connected through a contact hole made through the insulating layer and a wiring layer formed on the insulating layer. Examples of the material for the insulating layer include silicon oxide (SiO2), silicon nitride (SiN), SiON, SOG, NSG, BPSG, PSG, BSG and LTO.
In the nonvolatile memory according to any one of the first to fourth aspects of the present invention, practically, there can be employed a constitution in which such nonvolatile memories are combined as a pair (to be called xe2x80x9cnonvolatile memory-Axe2x80x9d and xe2x80x9cnonvolatile memory-Bxe2x80x9d for the sake of convenience), and the bit lines constituting the pair of the nonvolatile memories are connected to one sense amplifier. In this case, the transistor for selection constituting the nonvolatile memory-A and the transistor for selection constituting the nonvolatile memory-B may be connected to one word line or different word lines. Depending upon the constitution and operation method of the nonvolatile memory-A and the nonvolatile memory-B, 1 bit can be stored in each of the memory cells constituting the nonvolatile memory-A or the nonvolatile memory-B, or one memory cell constituting the nonvolatile memory-A and one memory cell constituting the nonvolatile memory-B and being connected to the plate line to which the above memory cell constituting the nonvolatile memory-A is connected can be combined as a pair so that complementary data can be stored in the pair of such memory cells.